8085 Timing Diagram

Introduction
Timing plays a crucial role, not only in sports like cricket but also in digital electronic equipments like microprocessors. Timing and Timing diagram plays a vital role in microprocessors.
What is a timing diagram? What role it plays with respect to microprocessors? Let’s discuss about these concepts in details.

What is a Timing Diagram?

The timing diagram is the diagram which provides information about the various conditions of signals such as high/low, when a machine cycle is being executed. Without the knowledge of timing diagram it is not possible to match the peripheral devices to the microprocessors. These peripheral devices includes memories, ports etc. Such devices can only be matched with microprocessors with the help of timing diagram.

Before dealing with timing diagram, we have to make ourselves familiar with certain terms.

Instruction cycle:
Assume that the microprocessor is executing an instruction. Instruction cycle is nothing but the time taken to complete the execution of that instruction by the microprocessor. The 8085 instruction cycle consists of 1 to 6 machine cycles.

Machine Cycle:
Machine cycle is nothing but the time required to complete one operation of accessing memory, I/O. It is also the time required to complete one operation of acknowledging an external request. One machine cycle may consist of 3 to 6 T-states.

T-state:
T-state is nothing but one subdivision of the operation performed in one clock period. These subdivisions are internal state of the microprocessor synchronized with system clock.


Now let us discuss the timing diagram for various signals that are associated with 8085 microprocessor.

Timing diagram of various signals

Address latch enable:
Address latch enable is an active high signal. (i.e.) the latch becomes enabled when the signal is high. It is activated during the beginning of T1 state of each machine cycle and it remains active in the T1state. But in case of bus idle machine cycle it is not activated.

Data Bus (D0-D7):
While dealing with data bus, two types of data flow are possible. The data can be transferred from memory to microprocessor and vice versa.

This process occurs during the T2 and T3 states.

There are 2 cycles. One is Read machine cycle and the other is write machine cycle. In read machine cycle, the data will appear during the later part of T2 state, while in Write machine cycle the data will appear on the beginning of T2 state.

But for reading a data from memory or I/O device, first we need to select the required device. After selecting the device, the required data to be read or written is taken from the selected location and placed on data bus. A certain amount of time is required to perform this action. This time is called “access time”. But for write cycle the access time is 0. This is because the data to be written is present on the registers of microprocessor and so it can put the data directly to data bus without any time delay.

Lower byte address (A0-A7):
The lower byte of address is available on the time multiplexed address/date bus during the T1 state of machine cycle, except the bus idle machine cycle.

Higher byte addresses (A8-A15):
The higher byte addresses (A8-A15) is available for T1, T2 and T3 states of each machine cycle, except the bus idle machine cycle.

IO/M’, S0, S1:
From the previous discussions about 8085 microprocessor, we very well know that IO/M’, S0, S1 are the status signals of the microprocessor. These status signals decide the type of machine cycle is to be executed. So they remain activated from the beginning T1 state of a particular machine cycle and remains till the end of that machine cycle.

RD’ and WR’:
These 2 signals RD’ and WR’ decides the direction of the data transfer.

RD’ is Active: When RD’ goes active, the data is transmitted from memory, I/O device or any other peripherals to the microprocessor.

WR’ is active: When WR’ goes active, the data is transmitted from microprocessor to the memory or any other peripheral devices.

Now there might be a question arising within your mind.

Can both the signals become active at same time? The answer for this question is NO.

In 8085 microprocessor either RD’ goes high or WR’ goes high. Both cannot take place at same time.

The data transfer both RD’ and WR’ takes place during T2 and T3 states of machine cycle. So these signals are activated during the T2 and T3 states.

8085 : Addressing Mode

Learn about the addressing modes of 8085 microprocessor, what are the different types of addressing modes available for 8085 microprocessor and the significance of the addressing modes explained with examples.

We have been doing a series of microprocessor education articles and till date we have discussed about the evolution of microprocessors, architecture, pin diagram and signal diagrams of 8085 microprocessor. We also discussed about how the signals helps in processing data, storing them and executing them.

But we cannot carry out a process with a microprocessor with only signals and instructions. We need a data to operate. Every instruction has to operate on a data.

There is a method in which the instructions address the data to be operated. The method of specifying the data to be operated by the instruction is known as addressing.
Now we know what is addressing. But what are addressing modes?

The way by which the microprocessor identifies the operands for a particular instruction is known as Addressing mode.

Types of Addressing Modes

The process of identifying the operands for a particular instruction can be carried out in several ways. The various types of addressing modes are as shown below.
1. Immediate addressing mode
2. Direct addressing mode
3. Register addressing mode
4. Register indirect addressing mode
5. Implicit addressing mode

Lets see the details:

1. Immediate Addressing Mode:
In this type of addressing mode the operand is specified within the instruction itself.
Let us discuss with an example.
Consider this instruction:
ADI 34H – This instruction adds the immediate data, 34H to the accumulator.
34H is the data here. H represents Hexadecimal value and the immediate value is added to the accumulator. In this case 34H is added to the accumulator. Suppose if accumulator has a value 8H and when this instruction is executed, 34H is added to the 8H and the result is stored in accumulator.
In the above instruction the operand is specified within instruction itself.

2. Direct Addressing Mode:
In this mode of addressing, the address of the data (operand) is specified within the instruction.
There is a subtle difference between the direct addressing modes and immediate addressing modes. In immediate addressing mode the data itself is specified within instruction, but in direct addressing mode the address of the data is specified in the instruction.
Example:
OUT 10H
LDA 4100H
STA 2000H
Consider the instruction STA 2000H
When this instruction is executed, the contents of the accumulator are stored in the memory location specified. In the above example the contents of accumulator are stored in memory location 2000H.

3. Register Addressing Mode:
In this type of addressing mode the instruction specifies the name of the register in which the data is available and Opcode specifies the name (or) address of the register on which the operation would be performed.
Example:
MOV A, B
Here the Opcode is MOV. If the above instruction is executed, the contents of Register B are moved to the Register A, which is nothing but the accumulator.

Other examples:
ANA B
On executing the above instruction the contents of Register B or logically ANDed with contents of register A (accumulator).
SUB H
If we execute the above instruction the contents of Register H will be subtracted from the contents of the accumulator.

4. Register Indirect Addressing Mode:
This is indirect way of addressing. In this mode the instruction specifies the name of the register in which the address of the data is available.
Example:
MOV A, M
SUB M
DCR M
Consider MOV A, M. This instruction will move the contents of memory location, whose address is in H-L register pair to the accumulator.
M represents the address present in the H-L register pair. So when MOV A, M is executed, the contents of the address specified in H-L register pair are moved to accumulator.

5. Implicit Addressing Mode:
There are certain instructions in 8085 which does not require the address of the operand to perform the operation. They operate only upon the contents of accumulator.
Example:
CMA
RAL
RAR
CMA complements the contents of accumulator.
If RAL is executed the contents of accumulator is rotated left one bit through carry.
If RAR is executed the contents of accumulator is rotated right one bit through carry.